EPC16QC100-TAAC80 vs EPC16QC100N 比較

詳細並排比較 EPC16QC100-TAAC80 由 Altera 與 EPC16QC100N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC16QC100-TAAC80 EPC16QC100N
品牌 Altera Altera
類別 Memory ICs Memory ICs
生命週期狀態 Obsolete Obsolete
記憶體類型 Flash (non-volatile configuration) —
Memory Density 16 Mbit —
Configuration Modes FPP, PS, AS, JTAG —
Data Compression Yes (built-in, 30-55% file size reduction) —
Supply Voltage (VCC) 3.3 V 3.0 V to 3.6 V
I/O Voltage Tolerance 1.8 V / 2.5 V / 3.3 V / 5 V —
Supported FPGA Families Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX
JTAG Support IEEE 1149.1 boundary scan, in-system programmable —
封裝 100-pin PQFP (Plastic Quad Flat Pack), 20x14 mm 100-pin PQFP (20 x 14 mm)
Package Code QC100 —
Packaging Style Tape and Reel (TAAC80 suffix) —
工作溫度 -40C to +85C (industrial) 0 C to 70 C
Configuration Controller Internal (integrated with flash array) —
腳位數 100 —
安裝類型 Surface Mount Surface Mount
記憶體容量 — 16 Mbit (16,777,216 bits)
Programmable Type — In System Programmable
Configuration Clock Frequency — 33 MHz max
On-Chip Decompression — Yes (supports compressed bitstreams)
Access Time — 90 ns typical
Flash Read Bandwidth — 160 Mbps (16-bit DQ at 10 MHz)
Configuration Interface — FPP / PS / AS via dedicated FPGA pins
JTAG (IEEE 1149.1) ISP — Supported
Lead Free — Yes (per datasheet)
Packaging — Tray

資料表與資源

瀏覽所有產品 建立 BOM 索取報價