EPC16QC100N vs EPC16JC88 比較

詳細並排比較 EPC16QC100N 由 Altera 與 EPC16JC88 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC16QC100N EPC16JC88
品牌 Altera Altera
類別 Memory ICs Memory ICs
生命週期狀態 Obsolete NRND
記憶體容量 16 Mbit (16,777,216 bits) —
Programmable Type In System Programmable —
Configuration Clock Frequency 33 MHz max —
On-Chip Decompression Yes (supports compressed bitstreams) —
Supply Voltage (VCC) 3.0 V to 3.6 V —
Access Time 90 ns typical —
Flash Read Bandwidth 160 Mbps (16-bit DQ at 10 MHz) —
Configuration Interface FPP / PS / AS via dedicated FPGA pins Altera/Intel serial configuration (DCLK / DATA0 / nCONFIG / nSTATUS / CONF_DONE)
JTAG (IEEE 1149.1) ISP Supported —
工作溫度 0 C to 70 C —
封裝 100-pin PQFP (20 x 14 mm) 88-ball UBGA (11 x 8 mm), JEDEC designation C88
安裝類型 Surface Mount —
Lead Free Yes (per datasheet) —
Packaging Tray —
Supported FPGA Families ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX Altera/Intel Stratix, Cyclone, APEX, Arria (via configuration interface)
Manufacturer — Altera (now Intel FPGA)
Family — Enhanced Configuration Device (EPC4 / EPC8 / EPC16)
Device Function — In-system programmable configuration PROM for SRAM-based FPGAs
Density — 16 Mbit
Programmability — In-system programmable via IEEE 1149.1 JTAG
Operating Temperature Grade — Industrial (J suffix)
供應電壓 — [DATA_NEEDED: VCC operating range]
Configuration Clock — Driven by target FPGA during configuration
Programming Interface — JTAG (IEEE 1149.1) 4-wire TCK/TMS/TDI/TDO
Multi-Device Configuration — Supports daisy-chain configuration of multiple FPGAs
濕度敏感等級 (MSL) — [DATA_NEEDED: MSL rating per JEDEC J-STD-020]
RoHS 狀態 — [DATA_NEEDED: RoHS compliance declaration]
Lead-Free — [DATA_NEEDED: lead-free finish]
無鹵素 — [DATA_NEEDED: halogen-free status]

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