EPC16QI100TBAC vs EPC16QC100 比較

詳細並排比較 EPC16QI100TBAC 由 Altera 與 EPC16QC100 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EPC16QI100TBAC EPC16QI100TBAC - Altera Enhanced Configuration PROM 16Mb | FPGA

EPC16QI100TBAC - Altera Enhanced Configuration PROM 16Mb | FPGA

EPC16QI100TBAC ⚠ 最後購買機會

規格比較

參數 EPC16QI100TBAC EPC16QC100
品牌 Altera Altera
類別 Memory ICs Memory ICs
生命週期狀態 最後購買 Obsolete
Memory Density 16 Mbit (2 Mbyte) —
記憶體類型 Flash (Enhanced Configuration Device) Flash Configuration PROM (non-volatile)
供應電壓 3.3 V —
Configuration Modes Passive Parallel Synchronous (PPS), Passive Parallel Asynchronous (PPA), Passive Serial (PS) —
Maximum Configuration Clock 40 MHz —
Number of Configuration Pages Up to 8 (selectable via PGM[2..0]) —
封裝 100-pin PQFP (20 x 14 mm) 100-pin PQFP (20 x 14 mm)
In-System Programmable Yes (via JTAG / IEEE 1149.1) —
JTAG Support Yes (IEEE 1149.1 boundary-scan and programming) —
Supported FPGA Families Altera Stratix, Cyclone, Arria series Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K
Data Compression Supported (15-30% density gain depending on target FPGA) —
工作溫度 -40C to +85C (industrial) -40C to +85C (commercial)
安裝類型 Surface Mount (PQFP) Surface Mount
MSL 等級 3 (168 hours) [DATA_NEEDED: MSL level]
Lead-Free / RoHS Lead-free (per JEDEC J-STD-020); RoHS compliance: [DATA_NEEDED] —
Dynamic Reconfiguration Yes (page mode via PGM[2..0] pins) —
Configuration Controller Integrated Integrated on-die
Programming Interface JTAG / 4-wire passive serial —
記憶體容量 — 16 Mbit
Configuration Clock (max) — 33 MHz
介面 — Altera enhanced configuration serial interface
In-System Programmability — Yes (IEEE 1149.1 JTAG)
Supply Voltage (VCC) — 3.0 V to 3.6 V
Cascadable — Yes (multi-device chain)
Compression Support — Yes (Altera enhanced compression)
RoHS 狀態 — [DATA_NEEDED: RoHS status]

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