EPC16T144C8N vs EPC16C100T 比較

詳細並排比較 EPC16T144C8N 由 Altera 與 EPC16C100T 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC16T144C8N EPC16C100T
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete NRND
Device Type Enhanced Configuration Device (FPGA boot memory) Enhanced Configuration Device
Memory Density 16 Mb —
Supply Voltage (VCC) 3.0 V to 3.6 V (3.3 V typical) —
Configuration I/O Voltage (VCCIO) 1.8 V / 2.5 V / 3.3 V / 5 V multi-voltage —
Configuration Mode Serial (AS) and Parallel (AP) —
JTAG Interface IEEE Std 1149.1 (IEEE 1532 ISP) —
In-System Programmability Yes (via JTAG) —
On-Chip Decompression Yes (compresses up to ~2x density) —
Speed Grade C8 (8 ns access time) —
工作溫度 0 C to +85 C (commercial) -40C to +85C (industrial)
封裝 144-LQFP (20 x 20 mm) 100-pin PQFP
安裝類型 Surface Mount Surface Mount
Compatible FPGA Families Altera Stratix, Cyclone, APEX series —
MSL 等級 [DATA_NEEDED: MSL level] —
RoHS 狀態 [DATA_NEEDED: RoHS compliance - likely compliant, not in data] —
Lead-Free / Halogen-Free [DATA_NEEDED: lead-free status] —
記憶體容量 — 16 Mb
Supported FPGAs — Stratix, Cyclone, APEX, Mercury (LUT-based)
Configuration Schemes — PS, PPS, FPP, PPA, JTAG
介面 — Serial / Parallel / JTAG (IEEE 1149.1)
Core Voltage — 3.3 V
I/O Voltage — 1.8 V to 3.3 V
Programmability — In-system via JTAG
Lead Pitch — 0.65 mm
Compression Support — Yes (Stratix / Stratix II)
Multi-Device Configuration — Yes (daisy chain)
Remote Update — Yes

資料表與資源

瀏覽所有產品 建立 BOM 索取報價