EPC1LC20CEC vs EPC1LC20-W 比較
詳細並排比較 EPC1LC20CEC 由 Altera 與 EPC1LC20-W 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC1LC20CEC | EPC1LC20-W |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | Obsolete | Obsolete |
| 記憶體類型 | OTP Configuration PROM (anti-fuse) | OTP (One-Time Programmable) Configuration PROM |
| 記憶體容量 | 1 Mbit (1,048,576 bits) | 1 Mbit |
| Configuration Interface | Serial (4-pin: DATA, DCLK, nCS, OE) | — |
| 最大時脈頻率 | 8 MHz | — |
| Programming Mode | One-Time Programmable (OTP) | — |
| 封裝 | 20-pin PLCC (9x9 mm) | 20-PLCC J-lead (9x9 mm) |
| 工作溫度 | 0°C to +70°C | — |
| 供應電壓 | [DATA_NEEDED: VCC range] | 3.3 V and 5.0 V |
| Configuration Mode | Altera serial slave/master | — |
| Compatible FPGA Families | ACEX 1K, APEX 20K, FLEX 6000, FLEX 8000, FLEX 10K | — |
| Read Endurance | Unlimited | — |
| Program Endurance | 1 cycle (OTP) | — |
| 安裝類型 | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket or direct solder) |
| RoHS 狀態 | Non-compliant (legacy PLCC package) | Compliant (Pb-free -W finish) |
| Lead-Free | No (contains lead) | — |
| Configuration Clock (DCLK) | — | 8 MHz maximum |
| 介面 | — | Altera serial configuration (DCLK / DATA / nCONFIG / nSTATUS) |
| In-System Programming | — | Yes - IEEE 1149.1 (JTAG) ISP at 3.3 V / 5.0 V |
| Lead Finish | — | Pb-free (matte tin) - "-W" suffix |
| Daisy-Chain Support | — | Yes - multiple EPC1 / EPC2 devices cascade to program larger FPGAs |
| Compression Support | — | Yes - stores compressed Altera FPGA bitstreams |
| 工作溫度範圍 | — | [DATA_NEEDED: operating temperature range] |
| Programming Cycles | — | 1 (OTP) |
| Target FPGA Families | — | Cyclone, FLEX 6000 / 10K / 10KE, ACEX 1K, APEX 20K, Mercury |