EPC2CC20N vs EPC2LC20N-W 比較

詳細並排比較 EPC2CC20N 由 Altera 與 EPC2LC20N-W 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC2CC20N EPC2LC20N-W
品牌 Altera Altera
類別 FPGA & CPLD Memory ICs
生命週期狀態 NRND Obsolete
功能 Configuration device for SRAM-based LUT FPGAs —
Density [DATA_NEEDED: bitstream density in bits] —
封裝 PLCC-20 20-LCC (J-Lead) PLCC-20
Configuration Interface 16-bit parallel (FPP) / Passive Serial (PS) Serial (DATA, DCLK, OE, nCS)
Supply Voltage (VCC) 3.3 V 3.0 V to 3.6 V, 4.75 V to 5.25 V
Programming Interface JTAG (IEEE 1149.1) via ByteBlasterMV / USB-Blaster —
In-System Programmable Yes —
Error Detection 16-bit CRC on configuration frames —
Configuration Modes Supported FPP and PS (depends on host FPGA) —
Cascadable Yes (multiple EPC2 devices for larger bitstreams) —
Open-Drain Status Pin Yes (CONF_DONE / nSTATUS compatible) —
工作溫度 [DATA_NEEDED: industrial/commercial temp range] [DATA_NEEDED: operating temperature range]
安裝類型 Surface Mount (PLCC-20 socket compatible) Surface Mount
MSL 等級 [DATA_NEEDED: MSL rating] —
RoHS 狀態 [DATA_NEEDED: RoHS compliance status] —
記憶體類型 — EPROM (UV-erasable, ISP)
記憶體容量 — 1.6 Mbit
Programmable Type — In System Programmable
Internal Oscillator Frequency — 66.7 MHz
ISP Interface — JTAG (IEEE 1149.1)
Supported FPGA Families — APEX 20K, ACEX 1K, Mercury, FLEX 10K, Stratix, Cyclone
Packaging — Tape & Reel (-W suffix)
Cascade Support — Yes (with other EPC2 devices)
腳位數 — 20
Lead-Free / RoHS — [DATA_NEEDED: RoHS status for -W variant]

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