EPC2LC20-U vs EPC2LC20N 比較
詳細並排比較 EPC2LC20-U 由 Altera 與 EPC2LC20N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC2LC20-U | EPC2LC20N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | Obsolete | NRND |
| 單價 (USD) | — | $7.40 |
| 記憶體類型 | Configuration PROM (Flash, in-system programmable) | Flash |
| 記憶體容量 | 1.6 Mbit | 1.6 Mbit |
| 介面 | Serial (4-wire Altera configuration) + JTAG (IEEE 1149.1) | Serial (DATA0, DCLK, nCONFIG, nSTATUS, CONF_DONE) |
| Max Configuration Clock | 10 MHz | — |
| Supply Voltage (VCC) | 3.3 V (3.0 V to 3.6 V) | — |
| Programmable | In-system via JTAG | — |
| Cascade Support | Yes (multi-PROM for larger bitstreams) | — |
| 封裝 | 20-PLCC (9x9) | 20-pin PLCC (J-Lead, 9x9 mm) |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | [DATA_NEEDED: full operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Supported FPGA Families | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K | Altera APEX, Cyclone, Stratix, ACEX, MAX 7000 |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | IEEE 1149.1 / IEEE 1532 compliant |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL 等級 | [DATA_NEEDED: moisture sensitivity level] | — |
| 功能 | — | In-System Programmable Configuration PROM for SRAM-based FPGAs |
| Programmable Type | — | In System Programmable (ISP) |
| Supply Voltage VCCINT | — | 3.0 V to 3.6 V |
| Supply Voltage VCCIO | — | 4.75 V to 5.25 V |
| Configuration Clock Frequency | — | 8 MHz (max) |
| Packaging | — | Tube |