EPC2LC20NU vs EPC2LC20N 比較

詳細並排比較 EPC2LC20NU 由 Altera 與 EPC2LC20N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC2LC20NU EPC2LC20N
品牌 Altera Intel
類別 Memory ICs Memory ICs
生命週期狀態 Obsolete NRND
單價 (USD) — $7.40
功能 In-System Programmable Configuration PROM In-System Programmable Configuration PROM for SRAM-based FPGAs
Memory Density 1.6 Mbit —
FPGA Interface Altera serial (4-pin: nCS, DCLK, DATA, nINIT_CONF) —
Supply Voltage (VCC) 3.0 V to 3.6 V —
I/O Tolerance 5 V tolerant inputs (per datasheet, except JTAG pins) —
Programming Method In-system via IEEE 1149.1 JTAG —
JTAG Support Yes (IEEE Std 1149.1 boundary-scan compliant) IEEE 1149.1 / IEEE 1532 compliant
Cascade Support Yes - daisy-chain for larger bitstreams —
Minimum DC Input -0.3 V (inputs may undershoot to -2.0 V for <20 ns) —
Maximum Overshoot 7.0 V for <100 mA and <20 ns —
封裝 20-pin J-lead PLCC (9x9 mm) 20-pin PLCC (J-Lead, 9x9 mm)
安裝類型 Surface Mount Surface Mount
Lead-Free / RoHS Non-LEAD / non-RoHS (NU suffix = matte tin Sn finish, not Pb-free) —
工作溫度 0C to +70C (commercial) [DATA_NEEDED: operating temperature range]
Compatibility Altera APEX 20K, APEX II, Mercury, FLEX 10K, ACEX 1K, Cyclone (legacy serial configuration) —
記憶體容量 — 1.6 Mbit
記憶體類型 — Flash
Programmable Type — In System Programmable (ISP)
Supply Voltage VCCINT — 3.0 V to 3.6 V
Supply Voltage VCCIO — 4.75 V to 5.25 V
Configuration Clock Frequency — 8 MHz (max)
介面 — Serial (DATA0, DCLK, nCONFIG, nSTATUS, CONF_DONE)
Packaging — Tube
Supported FPGA Families — Altera APEX, Cyclone, Stratix, ACEX, MAX 7000
RoHS 狀態 — [DATA_NEEDED: RoHS status]

資料表與資源

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