EPC2LC20NUBAF48 vs EPC2LC20N 比較
詳細並排比較 EPC2LC20NUBAF48 由 Altera 與 EPC2LC20N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC2LC20NUBAF48 | EPC2LC20N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | Memory ICs |
| 生命週期狀態 | Obsolete | NRND |
| 單價 (USD) | — | $7.40 |
| 記憶體類型 | Non-volatile flash configuration PROM | Flash |
| Memory Density | 2 Mbit (2,097,152 bits) | — |
| Core Supply Voltage (VCC) | 3.3 V (low-voltage 'L' variant) | — |
| I/O Logic Levels | 3.3 V LVCMOS (5V-tolerant inputs) | — |
| Configuration Interface | Altera serial (DATA, DCLK, nCS, ASDO) | — |
| JTAG / ISP Support | IEEE 1532 / JTAG in-system programming | — |
| Cascade Support | Yes - dedicated nCASC pin for 2-device chains | — |
| Programming Voltage | Internal 3.3V generation, no external VPP | — |
| FPGA Compatibility | APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, FLEX 6000 | — |
| 封裝 | 20-pin Ultra FineLine BGA (UBGA, NU suffix) | 20-pin PLCC (J-Lead, 9x9 mm) |
| 工作溫度 | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Configuration Clock | Internal oscillator (DCLK output to FPGA) | — |
| Programming Tools | Quartus II Programmer, ByteBlaster II, USB-Blaster | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| 功能 | — | In-System Programmable Configuration PROM for SRAM-based FPGAs |
| 記憶體容量 | — | 1.6 Mbit |
| Programmable Type | — | In System Programmable (ISP) |
| Supply Voltage VCCINT | — | 3.0 V to 3.6 V |
| Supply Voltage VCCIO | — | 4.75 V to 5.25 V |
| Configuration Clock Frequency | — | 8 MHz (max) |
| 介面 | — | Serial (DATA0, DCLK, nCONFIG, nSTATUS, CONF_DONE) |
| JTAG Support | — | IEEE 1149.1 / IEEE 1532 compliant |
| 安裝類型 | — | Surface Mount |
| Packaging | — | Tube |
| Supported FPGA Families | — | Altera APEX, Cyclone, Stratix, ACEX, MAX 7000 |