EPC2LI20N vs EPC2LC20-V 比較
詳細並排比較 EPC2LI20N 由 Altera 與 EPC2LC20-V 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC2LI20N | EPC2LC20-V |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | Obsolete | Obsolete |
| 記憶體類型 | Non-volatile configuration PROM (Flash) | Configuration PROM (Flash-based, in-system programmable) |
| 記憶體容量 | 1.6 Mbit | — |
| Programmable Type | In System Programmable (ISP via JTAG) | — |
| Configuration Mode | Serial | — |
| Maximum Configuration Frequency | 10 MHz | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V | — |
| Supply Voltage (VCCIO) | 4.5 V to 5.5 V | — |
| 封裝 / 外殼 | 20-PLCC (J-Lead), 9x9 mm | — |
| 安裝類型 | Surface Mount | Surface Mount (PLCC socket compatible) |
| Packaging | Tube | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | — |
| Supported FPGA Series | ACEX 1K, APEX II, Cyclone, Stratix II | — |
| JTAG Interface | IEEE 1149.1 boundary scan (TCK/TDI/TMS/TDO) | — |
| Configuration Pins | nCS, DCLK, DATA, nCONFIG, nSTATUS, CONF_DONE | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Compliant (per distributor listings) |
| Memory Density | — | 1.6 Mbit |
| Configuration Interface | — | Serial (Altera FPP/PS modes via DCLK/nSTATUS/CONF_DONE) |
| Maximum Configuration Clock | — | 10 MHz |
| Supply Voltage VCC | — | 3.3 V |
| I/O Tolerance | — | 5 V tolerant on configuration pins |
| In-System Programming | — | Yes, via IEEE 1149.1 JTAG (TMS/TCK/TDI/TDO) |
| Cascade Support | — | Yes, daisy-chainable for >1.6 Mbit designs |
| Operating Temperature Range (V suffix) | — | 0 °C to +70 °C (commercial) |
| Package Type | — | 20-pin PLCC (JEDEC MS-018) |
| Package Dimensions | — | 9 x 9 mm body, 1.27 mm pitch |
| Supported FPGA Families | — | APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, MAX 9000 |
| Lead-Free | — | Yes |