EPC2LI20NGA vs EPC2LC20 比較

詳細並排比較 EPC2LI20NGA 由 Altera 與 EPC2LC20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC2LI20NGA EPC2LC20
品牌 Altera Altera
類別 FPGA & CPLD Memory ICs
生命週期狀態 Obsolete NRND
單價 (USD) — $7.20
記憶體容量 1.6 Mbit 1.6 Mbit
功能 In-System Programmable Configuration PROM —
Target Device SRAM-based LUT FPGAs —
封裝 20-PLCC (9x9 mm) 20-pin PLCC (J-lead, 9x9 mm)
工作溫度範圍 -40C to +85C (Industrial) —
供應電壓 3.0 V to 3.6 V (3.3 V typical) —
Configuration Interface Passive Serial / Passive Parallel Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE
Programming Method In-System via JTAG (IEEE 1149.1) —
Cascadable Yes (DATA, DCLK chain) —
RoHS 狀態 Compliant (lead-free 'G' suffix) Non-Compliant (original Altera Pb-containing part)
安裝類型 Surface Mount / Thru-Hole Socket Surface Mount
Lead-Free Termination Yes (NiPdAu) —
Process Technology CMOS EEPROM —
Manufacturer Altera / Intel PSG —
Datasheet Document EPC2 datasheet (Altera) —
記憶體類型 — Non-volatile configuration PROM
Programming Interface — IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant
Supply Voltage VCC — 3.0 V to 3.6 V (3.3-V operation)
ISP Voltage Range — 5.0 V or 3.3 V
Supported FPGA Families — ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000
Cascade Support — Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams
工作溫度 — -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet]
Lead-Free Version — EPC2LC20N available as lead-free equivalent
Programming Support — Altera Programming Unit (APU), Quartus II, JTAG programmer
Boundary-Scan — IEEE 1149.1 compliant, 8-bit or 16-bit JTAG

資料表與資源

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