EPC2T32U-CAF48 vs EPC2LI20N 比較

詳細並排比較 EPC2T32U-CAF48 由 Altera 與 EPC2LI20N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC2T32U-CAF48 EPC2LI20N
品牌 Altera Altera
類別 Memory ICs Memory ICs
生命週期狀態 最後購買 Obsolete
記憶體類型 Non-volatile flash configuration memory Non-volatile configuration PROM (Flash)
Memory Density 2 Mb (2097152 bits) —
Configuration Interface Altera FPP (8-bit) / PS (4-wire) / AS (serial) —
Maximum Configuration Clock (DCLK) 8 MHz —
Supply Voltage (VCC) 3.3 V (typical) —
I/O Tolerance 5 V tolerant —
Program/Erase Endurance 10,000 cycles per sector minimum —
Data Retention 20 years minimum —
Programming Interface IEEE 1149.1 (JTAG) / IEEE 1532 —
封裝 48-pin QFN (CAF suffix) —
安裝類型 Surface Mount Surface Mount
工作溫度 -40 C to +85 C (industrial grade, "U") [DATA_NEEDED: operating temperature range]
MSL 等級 [DATA_NEEDED: MSL level] —
Lead-Free Finish Yes (CAF suffix indicates lead-free) —
RoHS 狀態 Compliant [DATA_NEEDED: RoHS status]
Supported FPGA Families Cyclone, Cyclone II, Stratix, APEX 20K, ACEX 1K, Mercury, Excalibur —
記憶體容量 — 1.6 Mbit
Programmable Type — In System Programmable (ISP via JTAG)
Configuration Mode — Serial
Maximum Configuration Frequency — 10 MHz
Supply Voltage (VCCINT) — 3.0 V to 3.6 V
Supply Voltage (VCCIO) — 4.5 V to 5.5 V
封裝 / 外殼 — 20-PLCC (J-Lead), 9x9 mm
Packaging — Tube
Supported FPGA Series — ACEX 1K, APEX II, Cyclone, Stratix II
JTAG Interface — IEEE 1149.1 boundary scan (TCK/TDI/TMS/TDO)
Configuration Pins — nCS, DCLK, DATA, nCONFIG, nSTATUS, CONF_DONE

資料表與資源

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