EPC2TC32V vs EPC2TC32 比較
詳細並排比較 EPC2TC32V 由 Altera 與 EPC2TC32 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC2TC32V | EPC2TC32 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | NRND | Obsolete |
| 記憶體類型 | In-System Programmable Configuration PROM | — |
| 記憶體容量 | 1.6 Mbit | 1.6 Mb |
| 組織 | x8 (configurable serial/parallel output) | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (3.3 V nominal) | — |
| I/O Voltage Tolerance | 5 V tolerant | — |
| 介面 | Passive Serial (PS), Passive Parallel Async (PPA), Passive Parallel Sync (PPS), JTAG ISP | Serial, JTAG, FPP, PS |
| Programming Method | In-system via JTAG (IEEE 1149.1) | — |
| Cascadable | Yes (multiple EPC2s daisy-chain for larger bitstreams) | — |
| 工作溫度 | 0 C to +70 C (commercial) | [DATA_NEEDED: operating temperature range] |
| 封裝 | 32-pin TQFP (7 mm x 7 mm) | 32-TQFP (7x7 mm) |
| 安裝類型 | Surface Mount | Surface Mount |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| Compatible FPGA Families | APEX 20K, APEX II, FLEX 10K/10KE, ACEX 1K, Cyclone (original), Stratix (original) | — |
| Configuration Hand-shake Pins | nCONFIG, nSTATUS, CONF_DONE, DCLK | — |
| RoHS 狀態 | Compliant | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | Yes | — |
| Device Type | — | In-System Programmable Configuration PROM |
| 供應電壓 | — | 3.3 V |
| Programmability | — | In-System Programmable (ISP) via JTAG |
| 腳位數 | — | 32 |
| Supported FPGA Families | — | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX |
| Configuration Modes | — | FPP, PS, JTAG |
| Internal Oscillator | — | Yes (DCLK generation) |
| Cascade Support | — | Yes (via nCS and RDYnBUSY) |
| Memory Technology | — | CMOS non-volatile |