EPC2XXA vs EPC2LI20 比較

詳細並排比較 EPC2XXA 由 Altera 與 EPC2LI20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC2XXA EPC2LI20
品牌 Altera Altera
類別 FPGA & CPLD Memory ICs
生命週期狀態 NRND NRND
記憶體類型 Configuration Flash (PROM) Flash (in-system programmable)
記憶體容量 1.6 Mbit 1.6 Mb (1,572,864 bits)
Configuration Interface Passive Serial (PS) / Active Serial (AS) Serial or Byte-wide (parallel)
Maximum Configuration Clock 33 MHz —
JTAG Support IEEE 1149.1 Boundary-Scan (ISP) —
Operating Voltage (VCC) 3.0 V to 3.6 V —
Operating Voltage (VCCJ) 1.8 V / 2.5 V / 3.3 V —
工作溫度 -40 C to +85 C (industrial) -40 C to +85 C (Industrial)
封裝 20-pin SOIC (SO-20) 12.8 mm x 7.5 mm —
安裝類型 Surface Mount Surface Mount (PLCC socket-compatible)
Cascadable Yes (daisy-chain multiple devices) —
Programmer Quartus II / Quartus Prime Programmer —
Compatible FPGA Families Cyclone, Cyclone II, Cyclone III, MAX II, MAX V, Stratix (selected) —
RoHS 狀態 Compliant [DATA_NEEDED: RoHS status]
Lead-Free Yes —
Programmable Type — In System Programmable (ISP)
功能 — Configuration PROM for SRAM-based FPGAs
Supply Voltage - Operating — 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing)
封裝 / 外殼 — 20-PLCC (J-lead, 9x9 mm)
Decompression — On-chip (supports compressed bitstreams)
JTAG / ISP Interface — IEEE 1532 (TCK, TMS, TDI, TDO)
Multi-Device Support — Yes (daisy-chain configuration)
User-Accessible Memory — Yes (unused flash available to user logic)
MSL 等級 — [DATA_NEEDED: MSL level]

資料表與資源

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