EPC4QC100 vs EPC4Q100N 比較

詳細並排比較 EPC4QC100 由 Altera 與 EPC4Q100N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC4QC100 EPC4Q100N
品牌 Altera Intel
類別 Memory ICs FPGA & CPLD
生命週期狀態 Obsolete NRND
功能 In-System Programmable Configuration PROM for FPGAs —
記憶體類型 Flash Flash (NOR, Enhanced Configuration Device)
記憶體容量 4 Mb 4 Mbit (512 Kbyte)
Supply Voltage (Core and I/O) 3.3 V —
Maximum Configuration Clock 66 MHz —
介面 Serial / Fast Passive (Altera FPGAs) —
In-System Programmability IEEE Std. 1532 compliant —
JTAG Support Yes (boundary scan + ISP via Jam STAPL) IEEE 1149.1 compliant
nINIT_CONF Pin Yes (triggers FPGA configuration via private JTAG instruction) —
封裝 100-pin PQFP (20x14 mm) 100-pin PQFP
工作溫度 0C to +70C (commercial) -40 C to +85 C (industrial)
安裝類型 Surface Mount Surface Mount
RoHS 狀態 unknown —
Lead-Free unknown —
Compatible FPGA Families Stratix, Cyclone, APEX, Mercury, ACEX —
Configuration Interface — Serial (FLEX) / Parallel / JTAG ISP
供應電壓 — 3.3 V
Program/Erase Cycles — [DATA_NEEDED: minimum endurance in cycles]
In-System Programmable — Yes
Target FPGA Families — Cyclone, Stratix, APEX, Mercury, ACEX
Data Width (parallel mode) — 8-bit
Lead-Free / RoHS — [DATA_NEEDED: per lot]
Status — Not Recommended for New Designs (NRND)
Configuration Schemes — Active Serial (AS) / Active Parallel (AP) / Passive Serial (PS)
MSL 等級 — [DATA_NEEDED: per JEDEC J-STD-020]

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