EPC4QC100N vs EPC4QC100 比較
詳細並排比較 EPC4QC100N 由 Intel 與 EPC4QC100 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC4QC100N | EPC4QC100 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | NRND | Obsolete |
| 記憶體類型 | Flash (NOR, configuration PROM) | Flash |
| 記憶體容量 | 4 Mbit (4,194,304 bits) | 4 Mb |
| Programmable Type | In System Programmable (ISP) | — |
| Configuration Interface | Serial / Parallel / JTAG (IEEE 1149.1) | — |
| Maximum DCLK Frequency | 66.7 MHz | — |
| On-Chip Decompression | Yes | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V | — |
| Typical Supply Voltage | 3.3 V | — |
| 工作溫度 | 0 C to 70 C (commercial) | 0C to +70C (commercial) |
| 封裝 | 100-pin PQFP (Plastic Quad Flat Pack) | 100-pin PQFP (20x14 mm) |
| Package Dimensions | 20 x 14 mm | — |
| Pin Pitch | 0.65 mm | — |
| 安裝類型 | Surface Mount | Surface Mount |
| Packaging | Tray | — |
| Lead Free / RoHS | Yes (per chipdig datasheet excerpt) | — |
| Family | EPC4 Enhanced Configuration Device | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | Yes (boundary scan + ISP via Jam STAPL) |
| 功能 | — | In-System Programmable Configuration PROM for FPGAs |
| Supply Voltage (Core and I/O) | — | 3.3 V |
| Maximum Configuration Clock | — | 66 MHz |
| 介面 | — | Serial / Fast Passive (Altera FPGAs) |
| In-System Programmability | — | IEEE Std. 1532 compliant |
| nINIT_CONF Pin | — | Yes (triggers FPGA configuration via private JTAG instruction) |
| RoHS 狀態 | — | unknown |
| Lead-Free | — | unknown |
| Compatible FPGA Families | — | Stratix, Cyclone, APEX, Mercury, ACEX |