EPC4QI100N vs EPC8QI100N 比較

詳細並排比較 EPC4QI100N 由 Altera 與 EPC8QI100N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC4QI100N EPC8QI100N
品牌 Altera Altera
類別 Memory ICs EEPROM
生命週期狀態 啟用中 NRND
單價 (USD) $10.40 —
記憶體類型 In-System Programmable Configuration PROM (NOR flash) —
記憶體容量 4 Mbit (4,194,304 bits) 8 Mbit (8,388,608 bits)
Programmable Type In System Programmable (ISP via JTAG) In System Programmable (Flash)
Supply Voltage (VCC) 3.0 V to 3.6 V 3.0 V to 3.6 V
介面 Altera serial (x1) configuration + JTAG —
Configuration Clock DCLK [DATA_NEEDED: DCLK maximum frequency] —
Active Supply Current (ICC active) [DATA_NEEDED: ICC active typical value] —
Standby Supply Current [DATA_NEEDED: ICC standby typical value] —
工作溫度 -40C to +85C (industrial) -40 °C to +85 °C (Industrial)
Storage Temperature -65C to +150C —
封裝 100-pin PQFP (PowerPQFP, 20x14 mm) 100-PQFP / 100-BQFP (20 x 14 mm)
Package Code QI100 (PQFP-100, industrial) —
安裝類型 Surface Mount Surface Mount
MSL 等級 [DATA_NEEDED: MSL rating] —
RoHS 狀態 [DATA_NEEDED: RoHS compliance] —
JTAG Standard IEEE 1149.1 boundary-scan / ISP —
Cascading Supported (multi-device daisy chain) —
Target FPGAs Altera Cyclone, Cyclone II, Stratix series —
Manufacturer — Altera (Intel)
Part Family — EPC8 (Enhanced Configuration)
Device Type — Configuration PROM for SRAM-based FPGAs
Configuration Interface — Altera serial (4-wire: DATA, DCLK, nCS, nINIT_CONF)
Maximum Configuration Clock — 50 MHz
On-Chip Decompression — Yes (Altera compression algorithm)
腳位數 — 100
Lead-Free / RoHS — Yes (per distributor listings)
JTAG (IEEE 1149.1) ISP — Supported
Multi-Device Daisy-Chain — Supported
Target FPGA Families — ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX
Packaging — Tray

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