EPC8Q100 vs EPC8QC100N 比較

詳細並排比較 EPC8Q100 由 Altera 與 EPC8QC100N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC8Q100 EPC8QC100N
品牌 Altera Intel
類別 FPGA & CPLD Memory ICs
生命週期狀態 Obsolete Obsolete
Memory Density 8 Mbit (8,388,608 bits) —
記憶體類型 NOR Flash, One-Time-Programmable (OTP) via JTAG Flash (NOR, configuration PROM)
Configuration Interface Altera EPC serial (DATA, DCLK, nCS, nINIT_CONF, nSTATUS, DONE) —
Supply Voltage VCC 5.0 V (3.3 V core generated on-chip) —
Internal Core Voltage 3.3 V (on-chip LDO) —
Maximum EPC Clock 33 MHz —
Programmability In-system via IEEE 1149.1 JTAG IEEE Std. 1532 in-system programmable (ISP)
FPGA Compatibility APEX 20K, APEX II, Cyclone, Cyclone II, Stratix, Stratix GX —
Configuration Mode Support FPP, PS, AS, JTAG (FPGA-dependent) —
Program/Erase Endurance [DATA_NEEDED: cycle count] —
Data Retention [DATA_NEEDED: minimum years] —
工作溫度範圍 0 C to +70 C (commercial) —
Storage Temperature Range [DATA_NEEDED: range] —
封裝 100-pin PQFP (20 x 14 mm) —
安裝類型 Surface Mount —
MSL 等級 [DATA_NEEDED: level] [DATA_NEEDED: Moisture Sensitivity Level]
Lead-Free / RoHS [DATA_NEEDED: status] —
記憶體容量 — 8 Mbit (8,388,608 bits)
組織 — 512K words x 16 bits
Configuration Device Family — EPC8 (Enhanced Configuration Device)
Supply Voltage (VCC) — 3.0 V to 3.6 V (typ. 3.3 V)
Maximum Configuration Clock — 66.7 MHz
Programming Interface — JTAG (IEEE 1149.1) + Jam STAPL
Package Type — Plastic Quad Flat Pack (PQFP-100)
腳位數 — 100
工作溫度 — 0 C to +70 C (commercial, N suffix)
nINIT_CONF Pin — Yes (private JTAG instruction to start FPGA configuration)
Compatible FPGAs — Altera Stratix, Stratix GX, Cyclone, APEX 20K series
RoHS 狀態 — [DATA_NEEDED: RoHS compliance status]

資料表與資源

瀏覽所有產品 建立 BOM 索取報價