EPC8Q100C vs EPC8Q100TBAC 比較

詳細並排比較 EPC8Q100C 由 Altera 與 EPC8Q100TBAC 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EPC8Q100C EPC8Q100C - 8Mb Enhanced Configuration Device | Altera/Intel

EPC8Q100C - 8Mb Enhanced Configuration Device | Altera/Intel

EPC8Q100C ⚠ 最後購買機會

規格比較

參數 EPC8Q100C EPC8Q100TBAC
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 最後購買 Obsolete
Memory Density 8 Mbit —
Device Family Enhanced Configuration Device (EPC8Q100 series) —
Configuration Interface Serial / Parallel (x8) slave mode —
供應電壓 3.3 V (typ) 3.3 V
In-System Programming IEEE 1149.1 JTAG —
封裝 100-pin PQFP (20 x 14 mm) QFP (TBAC suffix)
工作溫度 0 C to +70 C (commercial, 'C' suffix) Industrial grade (TBAC suffix)
Cascade Support Up to 4 devices cascadable —
Supported FPGA Families Altera Cyclone, Cyclone II, Stratix, Stratix GX, Apex series —
Configuration Clock User-programmable internal oscillator —
Programming Cycles 100 minimum endurance cycles —
Programming Voltage 3.3 V in-system (no external VPP) —
Lead-Free / RoHS Lead-free per Altera/Intel Pb-free roadmap —
安裝類型 Surface Mount (PQFP) Surface Mount
MSL 等級 [DATA_NEEDED: MSL rating] —
記憶體容量 — 8 Mb
記憶體類型 — Flash (non-volatile configuration storage)
Access Time — 90 ns (approximately 10 MHz flash read)
Flash Read Bandwidth — Approximately 160 Mbps (16-bit DQ[] at 10 MHz)
資料匯流排寬度 — 16-bit (DQ[])
Configuration Modes Supported — PS (Passive Serial), FPP (Fast Passive Parallel), PPA (Passive Parallel Asynchronous)
Programming Interface — IEEE 1532 / JTAG (in-system programmable)
Compatible FPGA Families — Altera Stratix, Cyclone, APEX, ACEX
RoHS 狀態 — [DATA_NEEDED: RoHS compliance status]
Lead-Free — [DATA_NEEDED: lead-free status]
Configuration Bitstream Compression — Supported (page-mode buffering)

資料表與資源

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