EPC8Q100TBAC vs EPC16QI100TBAC 比較

詳細並排比較 EPC8Q100TBAC 由 Intel 與 EPC16QI100TBAC 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EPC16QI100TBAC EPC16QI100TBAC - Altera Enhanced Configuration PROM 16Mb | FPGA

EPC16QI100TBAC - Altera Enhanced Configuration PROM 16Mb | FPGA

EPC16QI100TBAC ⚠ 最後購買機會

規格比較

參數 EPC8Q100TBAC EPC16QI100TBAC
品牌 Intel Altera
類別 FPGA & CPLD Memory ICs
生命週期狀態 Obsolete 最後購買
記憶體容量 8 Mb —
記憶體類型 Flash (non-volatile configuration storage) Flash (Enhanced Configuration Device)
Access Time 90 ns (approximately 10 MHz flash read) —
Flash Read Bandwidth Approximately 160 Mbps (16-bit DQ[] at 10 MHz) —
資料匯流排寬度 16-bit (DQ[]) —
供應電壓 3.3 V 3.3 V
Configuration Modes Supported PS (Passive Serial), FPP (Fast Passive Parallel), PPA (Passive Parallel Asynchronous) —
Programming Interface IEEE 1532 / JTAG (in-system programmable) JTAG / 4-wire passive serial
工作溫度 Industrial grade (TBAC suffix) -40C to +85C (industrial)
封裝 QFP (TBAC suffix) 100-pin PQFP (20 x 14 mm)
安裝類型 Surface Mount Surface Mount (PQFP)
Compatible FPGA Families Altera Stratix, Cyclone, APEX, ACEX —
RoHS 狀態 [DATA_NEEDED: RoHS compliance status] —
Lead-Free [DATA_NEEDED: lead-free status] —
Configuration Bitstream Compression Supported (page-mode buffering) —
Memory Density — 16 Mbit (2 Mbyte)
Configuration Modes — Passive Parallel Synchronous (PPS), Passive Parallel Asynchronous (PPA), Passive Serial (PS)
Maximum Configuration Clock — 40 MHz
Number of Configuration Pages — Up to 8 (selectable via PGM[2..0])
In-System Programmable — Yes (via JTAG / IEEE 1149.1)
JTAG Support — Yes (IEEE 1149.1 boundary-scan and programming)
Supported FPGA Families — Altera Stratix, Cyclone, Arria series
Data Compression — Supported (15-30% density gain depending on target FPGA)
MSL 等級 — 3 (168 hours)
Lead-Free / RoHS — Lead-free (per JEDEC J-STD-020); RoHS compliance: [DATA_NEEDED]
Dynamic Reconfiguration — Yes (page mode via PGM[2..0] pins)
Configuration Controller — Integrated

資料表與資源

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