EPC8QI100 vs EPC8QC100 比較

詳細並排比較 EPC8QI100 由 Intel 與 EPC8QC100 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC8QI100 EPC8QC100
品牌 Intel Altera
類別 Memory ICs Memory ICs
生命週期狀態 Obsolete Obsolete
記憶體類型 Flash (NOR, Enhanced Configuration PROM) Configuration PROM (Flash-based)
記憶體容量 8 Mbit 8 Mbit
Supply Voltage (Core) 3.3 V —
Supply Voltage (I/O) 3.3 V —
介面 Altera FPGA configuration serial/parallel (FPP) + JTAG (IEEE 1149.1) —
In-System Programmability IEEE Std. 1532 compliant —
Programming Language Jam STAPL —
Boundary Scan JTAG boundary-scan test supported —
Data Compression Yes (increases effective capacity) —
Configuration Controller On-chip, dedicated to Altera FPGAs —
Initiate-Configuration Pin nINIT_CONF (private JTAG instruction) —
工作溫度 -40C to +85C (industrial) 0C to +70C (Commercial)
封裝 100-PQFP (20 x 14 mm) 100-Pin PQFP (20 x 14 mm)
安裝類型 Surface Mount Surface Mount
Compatible FPGAs Stratix, Stratix II, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, Cyclone, Cyclone II, Arria GX, Stratix GX, Stratix II GX —
RoHS 狀態 Non-compliant (legacy PQFP, lead-bearing) [DATA_NEEDED: RoHS compliance]
Flash Access Time — 90 ns (~10 MHz)
Configuration Bus Width — 16-bit (DQ[])
Configuration Bandwidth — Up to 160 Mbps
Decompression Support — Yes (Altera proprietary)
Supported Configuration Modes — FPP, PS, AS (FPGA-dependent)
ISP Interface — JTAG (IEEE 1149.1)
供應電壓 — 3.3 V
Compatible FPGA Families — Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K
Lead Free — [DATA_NEEDED: lead-free status]

資料表與資源

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