EPF10K200SRC240-2 vs EPF10K200SRC240-2X 比較
詳細並排比較 EPF10K200SRC240-2 由 Intel 與 EPF10K200SRC240-2X 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPF10K200SRC240-2X - FLEX 10K 200K Gates 9984 Cells FPGA | Altera
EPF10K200SRC240-2X ⚠ 最後購買機會規格比較
| 參數 | EPF10K200SRC240-2 | EPF10K200SRC240-2X |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Series | FLEX 10KS | FLEX 10KS |
| Family | FLEX 10KS (FLEX 10KE/10KA generation) | FLEX 10KE |
| Number of Logic Elements (LEs) | 9984 | — |
| Number of Logic Array Blocks (LABs) | 1248 | — |
| Total RAM Bits | 98304 | — |
| Number of User I/Os | 182 | — |
| Number of Gates | 513000 | — |
| Core Supply Voltage | 2.375 V to 2.625 V (nominal 2.5 V) | — |
| 工作溫度 | 0C to +70C (Commercial, TA) | 0 C to +70 C (Commercial) |
| 封裝 / 外殼 | 240-BFQFP Exposed Pad (240-RQFP, 32x32 mm) | — |
| 安裝類型 | Surface Mount | Surface Mount |
| Terminal Form | GULL WING | — |
| Number of Terminals | 240 | — |
| Speed Grade | -2 (~80 MHz internal, typical) | -2X (industrial, upper-mid speed) |
| Configuration Interface | IEEE 1149.1 JTAG + Altera EPC EEPROM | — |
| Process Technology | 0.42 micrometer CMOS SRAM | CMOS |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | — |
| Logic Cells | — | 9984 |
| Logic Array Blocks (LABs) | — | 1248 |
| Equivalent Gates | — | 200,000 |
| Embedded RAM (approx.) | — | 98 Kbits |
| User I/Os (max in family) | — | 470 |
| User I/Os (this package) | — | 182 |
| Propagation Delay | — | 0.4 ns to 0.8 ns |
| Max Internal Frequency | — | 200 MHz |
| Core Voltage (VCCINT) | — | 2.5 V |
| I/O Voltage (VCCIO) | — | 3.3 V (banks; 5 V tolerant inputs) |
| 封裝 | — | RQFP-240 (240-pin Power Quad Flat Pack, 34.6 x 34.6 mm, 0.5 mm pitch) |
| Configuration Method | — | JTAG / Passive Serial (PS) |
| Boundary-Scan (JTAG) | — | IEEE 1149.1 compliant |
| Lead-Free / RoHS | — | [DATA_NEEDED: explicit lead-free status] |
| MSL 等級 | — | [DATA_NEEDED: moisture sensitivity level] |