EPF8820ARC208-2A vs EPF8820ARC208-3 比較
詳細並排比較 EPF8820ARC208-2A 由 Altera 與 EPF8820ARC208-3 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPF8820ARC208-2A - FLEX 8000 FPGA, 672 Logic Elements, 152 I/O | Altera
EPF8820ARC208-2A ObsoleteIntel
EPF8820ARC208-3 - FLEX 8000 FPGA, 8K Gates, 672 Cells | Intel / Altera
EPF8820ARC208-3 Obsolete規格比較
| 參數 | EPF8820ARC208-2A | EPF8820ARC208-3 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | FLEX 8000 | FLEX 8000 (EPF8820) |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| Logic Elements | 672 | — |
| Logic Array Blocks (LABs) | 84 | — |
| Embedded Array Blocks (EABs) | [DATA_NEEDED: EAB count] | — |
| User I/O Pins | 152 | — |
| Dedicated Inputs | 4 | — |
| Total RAM Bits | [DATA_NEEDED: distributed RAM bits] | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 5.0 V selectable | — |
| Propagation Delay (tPD) | 5 ns (typical, -2A speed grade) | — |
| 工作溫度 | 0 °C to 70 °C (commercial) | — |
| 封裝 | 208-pin S-PQFP (Shrink Plastic Quad Flat Pack) with exposed pad | — |
| Terminal Pitch | 0.500 mm | — |
| Configuration Method | Serial SRAM, EPC1/EPC1064/EPC1213/EPC1441 PROM, or controller | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | — |
| Process Technology | CMOS SRAM | 0.42 µm CMOS |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: check distributor listing] | [DATA_NEEDED: RoHS status] |
| Series | — | FLEX 8000 |
| Usable Gates | — | 8,000 |
| Logic Cells / Elements | — | 672 |
| Registers | — | 152 |
| Maximum Operating Frequency | — | 125 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Configuration Memory | — | SRAM (volatile) |
| 封裝 / 外殼 | — | 208-BFQFP Exposed Pad (208-RQFP, 28x28 mm) |
| Supplier Device Package | — | 208-RQFP (28x28) |
| Packaging | — | Tray |
| 工作溫度範圍 | — | [DATA_NEEDED: operating temperature range] |
| In-Circuit Reconfigurability (ICR) | — | Yes (via external configuration devices) |
| Boundary-Scan Test | — | JTAG (IEEE 1149.1) |
| I/O Tolerance | — | 3.3 V / 5 V |
| Clock Networks | — | 4 dedicated low-skew global clocks |
| Lead-Free / Finish | — | [DATA_NEEDED: lead-free finish] |