EPM240GF100C5N vs EPM240F100C5N 比較
詳細並排比較 EPM240GF100C5N 由 Intel 與 EPM240F100C5N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM240GF100C5N | EPM240F100C5N |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Family | MAX II | — |
| Logic Elements / Macro Cells | 192 macro cells | — |
| Pin-to-Pin Logic Delay (tPD) | 4.7 ns | 4.7 ns |
| Maximum Operating Frequency | 201.1 MHz | [DATA_NEEDED: fmax per datasheet] |
| User I/Os | 80 | — |
| Logic Family | CMOS | — |
| Process Technology | 0.18 um | — |
| Core Supply Voltage (VCCINT) | 1.8 V | — |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| User Flash Memory | 8 Kbits | — |
| 封裝 | 100-ball FBGA (11 x 11 mm, 1.0 mm pitch) | 100-ball FineLine BGA (FBGA-100) |
| 安裝類型 | Surface Mount | Surface Mount (BGA) |
| 工作溫度 | -40 C to +125 C | — |
| Programming Interface | JTAG (IEEE 1149.1) / Jam STAPL | JTAG / ByteBlasterMV |
| Configuration Memory | On-chip non-volatile Flash | Non-volatile flash (instant-on) |
| RoHS 狀態 | Lead Free, RoHS compliant | Compliant |
| Device Family | — | MAX II |
| Logic Elements (LEs) | — | 240 |
| Macrocells | — | 192 |
| User I/O Pins (maximum) | — | 80 |
| Global Clock Networks | — | [DATA_NEEDED: count] |
| 工作溫度範圍 | — | 0C to +85C (commercial) |
| Supply Voltage Core (VCCINT) | — | 3.3 V |
| I/O Bank Voltage (VCCIO) | — | 1.5V / 1.8V / 2.5V / 3.3V (MultiVolt) |
| JTAG Support | — | IEEE 1149.1 boundary-scan |