EPM240GF100C5N vs EPM570GF100C5N 比較

詳細並排比較 EPM240GF100C5N 由 Intel 與 EPM570GF100C5N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EPM570GF100C5N EPM570GF100C5N - MAX II 570 LE CPLD, 100-FBGA | Altera

EPM570GF100C5N - MAX II 570 LE CPLD, 100-FBGA | Altera

EPM570GF100C5N ✓ 啟用中

規格比較

參數 EPM240GF100C5N EPM570GF100C5N
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 啟用中
Family MAX II —
Logic Elements / Macro Cells 192 macro cells —
Pin-to-Pin Logic Delay (tPD) 4.7 ns —
Maximum Operating Frequency 201.1 MHz —
User I/Os 80 76
Logic Family CMOS —
Process Technology 0.18 um —
Core Supply Voltage (VCCINT) 1.8 V —
I/O Supply Voltage (VCCIO) 1.5 V / 1.8 V / 2.5 V / 3.3 V —
User Flash Memory 8 Kbits —
封裝 100-ball FBGA (11 x 11 mm, 1.0 mm pitch) 100-LBGA (FBGA-100), 11 x 11 mm, 1.0 mm pitch
安裝類型 Surface Mount Surface Mount
工作溫度 -40 C to +125 C -40C to +125C (industrial)
Programming Interface JTAG (IEEE 1149.1) / Jam STAPL IEEE 1532 / JTAG (IEEE 1149.1) ISP
Configuration Memory On-chip non-volatile Flash On-chip Flash (non-volatile)
RoHS 狀態 Lead Free, RoHS compliant Compliant (lead-free)
Device Family — MAX II
Logic Elements — 570
Macrocells — 440
Propagation Delay (tPD) — 5.4 ns
Core Voltage — 1.8 V (internal)
I/O Voltage Support — 1.8 V / 2.5 V / 3.3 V (5.0 V tolerant inputs)
Logic Family / Process — CMOS, Flash-based LUT
LABs — 4 (16 macrocells per LAB)

資料表與資源

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