EPM240GT100C4N vs EPM240GM100C5N 比較
詳細並排比較 EPM240GT100C4N 由 Intel 與 EPM240GM100C5N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM240GM100C5N - 192-Cell MAX II G CPLD, 4.7ns, 100-MBGA | Intel / Altera
EPM240GM100C5N ✓ 啟用中規格比較
| 參數 | EPM240GT100C4N | EPM240GM100C5N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Family | MAX II | MAX II G |
| Logic Elements | 240 | 240 (192 macrocells) |
| Macro Cells | 192 | — |
| Maximum User I/O | 80 | — |
| On-chip Flash Memory | 8 Kbits | — |
| Core Voltage | 1.8 V | — |
| I/O Voltage Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V | 1.5 V / 1.8 V / 2.5 V / 3.3 V (multiVolt) |
| Maximum Operating Frequency | 247.5 MHz | — |
| Propagation Delay (tPD) | 6.1 ns | — |
| Speed Grade | C4 | — |
| Process Technology | 0.18 µm 6-layer metal flash | CMOS, Flash-based |
| 封裝 | TQFP-100 (16 × 16 mm, 0.5 mm pitch) | 100-MBGA (Micro FineLine BGA), 6 x 6 mm |
| 安裝類型 | Surface Mount | Surface Mount (BGA) |
| Programmability | JTAG (IEEE 1149.1) ISP | — |
| RoHS 狀態 | Lead-Free / Compliant | — |
| User I/Os | — | 80 |
| Pin-to-Pin Delay (tPD) | — | 4.7 ns |
| Ball Pitch | — | 0.5 mm |
| Supply Voltage - Core | — | 3.3 V |
| Programming Interface | — | JTAG (IEEE 1149.1) - ISP |
| Configuration Memory | — | Non-volatile Flash |
| 工作溫度 | — | -40 C to +125 C |
| Lead Free / RoHS | — | Yes / Compliant |
| MSL 等級 | — | 3 |