EPM240T100A5N vs EPM240GT100C4 比較
詳細並排比較 EPM240T100A5N 由 Altera 與 EPM240GT100C4 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM240T100A5N | EPM240GT100C4 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Family | MAX II | MAX II |
| Macro Cells | 192 | — |
| Logic Elements (LE) | 240 | 240 |
| User I/O Count | 80 | — |
| Pin-to-Pin Logic Delay (tPD) | 4.7 ns | — |
| Maximum Internal Frequency | 201.1 MHz | — |
| 供應電壓 | 2.5 V / 3.3 V | — |
| I/O Bank Count | 4 (multi-voltage) | — |
| Process Technology | 0.18 µm | 0.18-µm, 6-layer-metal flash CMOS |
| Configuration Memory | On-chip Flash (instant-on) | — |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG (IEEE 1149.1) / In-System Programmable (ISP) |
| 封裝 | 100-pin TQFP (14 x 14 x 1.0 mm) | 100-TQFP (TQFP-100), 16 x 16 mm, 0.5 mm pitch |
| 工作溫度 | 0C to +85C (commercial, "A5N" suffix) | — |
| 安裝類型 | Surface Mount | Surface Mount (Gull-Wing leads) |
| RoHS 狀態 | Compliant (Pb-free) | — |
| Equivalent Macrocells | — | 192 |
| Pin-to-Pin Delay (tPD) | — | 4.7 ns |
| Propagation Delay | — | 6.1 ns (max) |
| User I/O Pins (max) | — | 80 |
| On-chip Flash Memory (UFM) | — | 8 Kbits |
| I/O Standards Supported | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V (MultiVolt) |
| 工作溫度範圍 | — | 0°C to +85°C (Commercial) |
| Supply Voltage (Core) | — | 3.3 V |
| Lead-Free / RoHS | — | Lead-Free (per FindIC entry); RoHS compliance [DATA_NEEDED: verify against manufacturer datasheet] |