EPM3032ALC44-10N vs EPM3032ALC44-7N 比較

詳細並排比較 EPM3032ALC44-10N 由 Altera 與 EPM3032ALC44-7N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM3032ALC44-10N EPM3032ALC44-7N
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 NRND NRND
Family MAX 3000A —
Product Type CPLD (Complex Programmable Logic Device) —
Logic Gates 600 gates 600 usable gates
Macrocells 32 —
Logic Array Blocks (LABs) 2 —
User I/O Pins 34 —
Propagation Delay (tPD) 10 ns —
Internal fMAX 103.1 MHz —
Supply Voltage (VCCINT) 3.3 V —
I/O Voltage (VCCIO) 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) —
Technology CMOS EEPROM-based —
In-System Programmability Yes, via IEEE 1149.1 JTAG —
ISP Standard Compliance IEEE Std. 1532 —
Boundary-Scan Test (BST) Yes, IEEE 1149.1 compliant —
封裝 44-pin PLCC (J-Lead, surface mount) 44-PLCC (J-Lead, 16.59 x 16.59 mm)
安裝類型 Surface Mount Surface Mount (PLCC socket compatible)
工作溫度 [DATA_NEEDED: industrial/commercial range] 0C to +70C (commercial grade)
RoHS 狀態 [DATA_NEEDED: compliant or non-compliant] [DATA_NEEDED: RoHS compliance status]
Manufacturer — Altera (Intel)
Series — MAX 3000A
Device Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 32
Propagation Delay (tPD1) — 7.5 ns (max, pin-to-pin)
Internal Counter Frequency (fCNT) — 227.3 MHz (max)
Number of Logic Elements / Blocks — 2 LABs (16 macrocells each)
Number of I/O Pins — 34 usable I/O (44 total package pins)
Number of Dedicated Inputs — 4
Programmable Type — In-System Programmable (ISP) via JTAG (IEEE 1149.1)
記憶體類型 — EEPROM (non-volatile, 100 program/erase cycles)
Supply Voltage - Internal (VCCINT) — 3.0 V to 3.6 V (3.3 V typical)
I/O Bank Voltage (VCCIO) — MultiVolt: 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant
MSL 等級 — 3 (168 hours)
Process Technology — CMOS EEPROM

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