EPM3032ALC44-7N vs EPM3064ALC44-7N 比較

詳細並排比較 EPM3032ALC44-7N 由 Altera 與 EPM3064ALC44-7N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM3032ALC44-7N EPM3064ALC44-7N
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 NRND 最後購買
Manufacturer Altera (Intel) —
Series MAX 3000A —
Device Type CPLD (Complex Programmable Logic Device) —
Macro Cells 32 —
Logic Gates 600 usable gates —
Propagation Delay (tPD1) 7.5 ns (max, pin-to-pin) —
Internal Counter Frequency (fCNT) 227.3 MHz (max) —
Number of Logic Elements / Blocks 2 LABs (16 macrocells each) —
Number of I/O Pins 34 usable I/O (44 total package pins) —
Number of Dedicated Inputs 4 —
Programmable Type In-System Programmable (ISP) via JTAG (IEEE 1149.1) —
記憶體類型 EEPROM (non-volatile, 100 program/erase cycles) —
Supply Voltage - Internal (VCCINT) 3.0 V to 3.6 V (3.3 V typical) —
I/O Bank Voltage (VCCIO) MultiVolt: 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant —
工作溫度 0C to +70C (commercial grade) 0C to +70C (commercial)
封裝 44-PLCC (J-Lead, 16.59 x 16.59 mm) 44-pin PLCC
安裝類型 Surface Mount (PLCC socket compatible) Surface Mount (PLCC socket compatible)
MSL 等級 3 (168 hours) —
RoHS 狀態 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Process Technology CMOS EEPROM —
Family — MAX 3000A
Logic IC Type — CPLD (Complex Programmable Logic Device)
Macrocells — 64
Logic Array Blocks (LABs) — 2
Usable Gates — 1,250
Number of User I/O Pins — 34
Pin-to-Pin Delay (tPD) — 7.5 ns
Maximum Frequency — 135.1 MHz
Core Technology — CMOS EEPROM
Supply Voltage (VCCINT) — 3.3 V
I/O Tolerance — 5 V-tolerant
In-System Programmability — Yes (IEEE Std 1149.1 JTAG)
Programming Software — Quartus II / Quartus Prime (legacy MAX+PLUS II supported)

資料表與資源

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