EPM3064AT100-10N vs EPM3064ATI100-10N 比較
詳細並排比較 EPM3064AT100-10N 由 Altera 與 EPM3064ATI100-10N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM3064AT100-10N | EPM3064ATI100-10N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | 啟用中 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | 4 |
| Usable Gates | 1,250 | 1,250 |
| User I/O Pins | 66 | — |
| Speed Grade | -10 (10 ns pin-to-pin delay) | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Bank Voltage | 3.3 V | — |
| 5 V Tolerant Inputs | Yes (via clamping diodes) | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| Programming Interface | JTAG (IEEE Std. 1149.1) with pin-locking | — |
| ISP Compliance | IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | IEEE Std. 1149.1 compliant | — |
| 封裝 | TQFP-100 (T100), 14 mm x 14 mm | 100-pin TQFP (industrial) |
| Operating Temperature (Commercial) | 0C to +70C | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | RoHS Non-Compliant |
| Lead-Free | [DATA_NEEDED: lead-free finish] | — |
| Programmable Type | — | In-System Programmable (ISP) via IEEE 1149.1 JTAG |
| Technology | — | CMOS EEPROM |
| User I/O | — | 66 |
| Supply Voltage (Core / I/O) | — | 3.3 V |
| Pin-to-Pin Delay (tPD) | — | 10 ns (-10 speed grade) |
| Maximum Internal Frequency | — | 227.3 MHz (counter) |
| 工作溫度 | — | -40 C to +85 C (industrial) |
| JTAG (IEEE 1149.1) | — | Yes |
| PCI Compliance | — | PCI Local Bus Specification Revision 2.2 (-4/-5/-6/-7/-10 speed grades) |
| MultiVolt I/O | — | Supports 2.5 V / 3.3 V / 5 V mixed-voltage interfacing |
| Lead-Free Status | — | Contains Lead |