EPM3064ATC100-10NA vs EPM3064ATC100-7N 比較
詳細並排比較 EPM3064ATC100-10NA 由 Intel 與 EPM3064ATC100-7N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EPM3064ATC100-10NA - MAX 3000A CPLD, 64 Macrocells, 10ns, TQFP-100 | Intel (Altera)
EPM3064ATC100-10NA ✓ 啟用中規格比較
| 參數 | EPM3064ATC100-10NA | EPM3064ATC100-7N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | NRND |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macrocells | 64 | 64 |
| User I/Os | 66 | — |
| Usable Gates | 1,250 | up to 1,250 |
| Logic Array Blocks (LABs) | 4 | 2 |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Operating Frequency | [DATA_NEEDED: fMAX in MHz] | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| MultiVolt I/O Voltages | 2.5 V / 3.3 V / 5.0 V | — |
| 封裝 | TQFP-100 (0.5 mm pitch) | TQFP-100 |
| Configuration Memory | Non-volatile EEPROM | — |
| In-System Programming | IEEE Std. 1532 compliant | IEEE Std. 1149.1 (JTAG), IEEE Std. 1532 |
| Boundary-Scan Test | IEEE Std. 1149.1 (JTAG) | — |
| 工作溫度 | 0C to +70C (commercial) | 0 °C to +70 °C (commercial) |
| Lead-Free / RoHS | Yes (NA suffix) | — |
| User I/O Pins | — | 66 |
| Propagation Delay (tPD) | — | 7.5 ns (pin-to-pin, -7 speed grade) |
| Maximum Internal Frequency | — | 166.7 MHz (-7 speed grade) |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V or 2.5 V |
| Program Memory Technology | — | EEPROM (non-volatile) |
| 安裝類型 | — | Surface Mount |
| RoHS 狀態 | — | [DATA_NEEDED: confirmed RoHS status from manufacturer page] |