EPM3064ATC44-10 vs EPM3064ALC44-10N 比較

詳細並排比較 EPM3064ATC44-10 由 Altera 與 EPM3064ALC44-10N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM3064ATC44-10 EPM3064ALC44-10N
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family MAX 3000A —
Logic Elements / Macrocells 64 macrocells —
Usable Gates 1,250 1,250
Number of Logic Blocks / LABs 4 LABs —
Propagation Delay (tPD) 10 ns 10 ns
Maximum Internal Frequency 227.3 MHz (counter speed) —
Programmable I/Os 34 —
Supply Voltage (VCCINT) 3.0 V to 3.6 V (3.3 V typical) 3.0 V to 3.6 V
I/O Bank Voltage (VCCIO) MultiVolt 1.5 V / 1.8 V / 2.5 V / 3.3 V 3.0 V to 3.6 V (MultiVolt)
Technology CMOS EEPROM, 5 V tolerant I/O —
In-System Programming IEEE Std. 1532 (JTAG) —
Boundary-Scan Support IEEE 1149.1 (JTAG) —
封裝 TQFP-44, 10 x 10 mm, 0.8 mm pitch 44-pin PLCC (LC44)
安裝類型 Surface Mount Surface Mount (PLCC socket compatible)
工作溫度範圍 0C to +70C (commercial) —
RoHS 狀態 Non-compliant (legacy Altera, Pb-bearing) Compliant
Product Family — MAX 3000A
Device Type — CPLD (Complex Programmable Logic Device)
Macrocells — 64
Logic Array Blocks (LABs) — 4
User I/O Pins — 34
Maximum Counter Frequency — 227.3 MHz
Configuration Memory — CMOS EEPROM
In-System Programmability — Yes (IEEE 1149.1 JTAG, IEEE 1532 compliant)
工作溫度 — [DATA_NEEDED: commercial / industrial grade]
Open-Drain Output Option — Yes (per I/O pin)
Output Slew-Rate Control — Programmable

資料表與資源

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