EPM3064ATC44-7N vs EPM3064ATI44-7N 比較

詳細並排比較 EPM3064ATC44-7N 由 Altera 與 EPM3064ATI44-7N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM3064ATC44-7N EPM3064ATI44-7N
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete NRND
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macro Cells 64 —
Logic Array Blocks 2 —
Usable Gates 1,250 1,250 gates
User I/O Pins 34 —
腳位數 44 —
Speed Grade -7 (7.5 ns pin-to-pin delay) —
Pin-to-Pin Delay (tPD) 7.5 ns —
Maximum Counter Frequency 192.3 MHz (-7 grade) —
Supply Voltage (VCC) 3.3 V —
MultiVolt I/O 1.8 V / 2.5 V / 3.3 V —
Programmability EEPROM, in-system programmable (ISP) —
JTAG Interface IEEE Std. 1149.1 compliant —
ISP Standard IEEE Std. 1532 compliant —
Boundary-Scan Test (BST) Built-in, JTAG-driven —
封裝 44-pin TQFP 44-pin TQFP (10x10 mm, 0.8 mm pitch)
工作溫度 0°C to +85°C (commercial) —
安裝類型 Surface Mount —
RoHS 狀態 Compliant Compliant (lead-free, 'N' suffix)
Logic Elements / Macrocells — 64 macrocells
Maximum Frequency (fMAX) — 135.1 MHz
Pin-to-Pin Logic Delay — 7 ns (speed grade -7)
User I/O Count — 34 I/O
Dedicated Input Pins — 4
Supply Voltage (VCCINT) — 3.3 V
I/O Bank Voltage (VCCIO) — 1.8 V / 2.5 V / 3.3 V / 5 V tolerant (multiVolt)
Program Memory Type — EEPROM (in-system programmable)
Programming Interface — IEEE 1149.1 JTAG
Operating Temperature Grade — Industrial (-40C to +85C)
Process Technology — 0.30 µm CMOS EEPROM

資料表與資源

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