EPM3128ATC144-10N vs EPM3128ATC144-7N 比較

詳細並排比較 EPM3128ATC144-10N 由 Intel 與 EPM3128ATC144-7N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM3128ATC144-10N EPM3128ATC144-7N
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 啟用中
單價 (USD) — $9.25
Family MAX 3000A —
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macro Cells 128 —
Usable Gates 2,500 (up to 10,000 for full family) —
Logic Array Blocks (LABs) 8 —
User I/Os 96 96
Propagation Delay (tPD) 10 ns (speed grade -10) 7.5 ns (pin-to-pin, -7 speed grade)
Counter Frequency (fCNT) 98 MHz —
Supply Voltage (VCCINT/VCCIO) 3.3 V —
MultiVolt I/O Support 3.3 V / 2.5 V / 1.8 V —
Configuration Memory EEPROM (in-system programmable, non-volatile) —
封裝 144-pin TQFP TQFP-144 (20 x 20 mm, 0.5 mm pitch)
安裝類型 Surface Mount Surface Mount (SMD/SMT)
工作溫度 0 °C to +70 °C (commercial) 0 °C to +70 °C (commercial)
JTAG (IEEE 1149.1) Yes (BST + pin-locking) —
ISP (IEEE 1532) Yes —
Series — MAX 3000A
Architecture — EEPROM-based, MAX architecture
Number of Macrocells — 128
Number of Usable Gates — Up to 10,000
腳位數 — 144
Logic Family — CMOS
Counter Frequency — Up to 227.3 MHz
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 2.5 V / 3.3 V / 5.0 V (MultiVolt)
In-System Programmability (ISP) — Yes, via JTAG (IEEE 1149.1)
PCI Compliance — Compatible with PCI Local Bus Specification Rev. 2.2
RoHS 狀態 — Lead-free (-7N suffix indicates Pb-free finish)

資料表與資源

瀏覽所有產品 建立 BOM 索取報價