EPM3128ATC144-10N vs EPM3128ATC144-7N 对比

详细并排对比 EPM3128ATC144-10N 出自 Intel 和 EPM3128ATC144-7N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3128ATC144-10N EPM3128ATC144-7N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 有效
库存状态 有库存 有库存
单价(USD) $6.56 $9.25
Family MAX 3000A —
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macro Cells 128 —
Usable Gates 2,500 (up to 10,000 for full family) —
Logic Array Blocks (LABs) 8 —
User I/Os 96 96
Propagation Delay (tPD) 10 ns (speed grade -10) 7.5 ns (pin-to-pin, -7 speed grade)
Counter Frequency (fCNT) 98 MHz —
Supply Voltage (VCCINT/VCCIO) 3.3 V —
MultiVolt I/O Support 3.3 V / 2.5 V / 1.8 V —
Configuration Memory EEPROM (in-system programmable, non-volatile) —
封装 144-pin TQFP TQFP-144 (20 x 20 mm, 0.5 mm pitch)
安装类型 Surface Mount Surface Mount (SMD/SMT)
工作温度 0 °C to +70 °C (commercial) 0 °C to +70 °C (commercial)
JTAG (IEEE 1149.1) Yes (BST + pin-locking) —
ISP (IEEE 1532) Yes —
Series — MAX 3000A
Architecture — EEPROM-based, MAX architecture
Number of Macrocells — 128
Number of Usable Gates — Up to 10,000
引脚数量 — 144
Logic Family — CMOS
Counter Frequency — Up to 227.3 MHz
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 2.5 V / 3.3 V / 5.0 V (MultiVolt)
In-System Programmability (ISP) — Yes, via JTAG (IEEE 1149.1)
PCI Compliance — Compatible with PCI Local Bus Specification Rev. 2.2
RoHS 状态 — Lead-free (-7N suffix indicates Pb-free finish)

数据手册与资源

浏览全部产品 创建 BOM 获取报价