EPM3128ATC144-7N vs EPM3128ATI144-5N 比較
詳細並排比較 EPM3128ATC144-7N 由 Altera 與 EPM3128ATI144-5N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM3128ATC144-7N | EPM3128ATI144-5N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | NRND |
| 單價 (USD) | $9.25 | — |
| Series | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Architecture | EEPROM-based, MAX architecture | — |
| Number of Macrocells | 128 | — |
| Number of Usable Gates | Up to 10,000 | — |
| User I/Os | 96 | 96 |
| 腳位數 | 144 | — |
| 封裝 | TQFP-144 (20 x 20 mm, 0.5 mm pitch) | TQFP-144 (20x20 mm, 0.5 mm pitch) |
| Logic Family | CMOS | — |
| Propagation Delay (tPD) | 7.5 ns (pin-to-pin, -7 speed grade) | — |
| Counter Frequency | Up to 227.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| 工作溫度 | 0 °C to +70 °C (commercial) | -40C to +85C (industrial) |
| In-System Programmability (ISP) | Yes, via JTAG (IEEE 1149.1) | — |
| PCI Compliance | Compatible with PCI Local Bus Specification Rev. 2.2 | — |
| 安裝類型 | Surface Mount (SMD/SMT) | Surface Mount |
| RoHS 狀態 | Lead-free (-7N suffix indicates Pb-free finish) | [DATA_NEEDED: RoHS status] |
| Family | — | MAX 3000A |
| Logic Gates | — | 2,500 gates |
| Macro Cells | — | 128 |
| Maximum Operating Frequency | — | 192.3 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 5.0 ns |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V (3.3 V nominal) |
| I/O Standard | — | LVCMOS / LVTTL (5.0 V tolerant inputs) |
| Programming Interface | — | JTAG (IEEE 1149.1 BST) - in-system |
| Process Technology | — | 0.30 um CMOS EEPROM |
| Configuration Memory | — | Non-volatile on-chip EEPROM |
| MSL 等級 | — | 3 (168 hours) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |