EPM3128ATI144-10 vs EPM3128ATC144-5N 比較

詳細並排比較 EPM3128ATI144-10 由 Altera 與 EPM3128ATC144-5N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EPM3128ATC144-5N EPM3128ATC144-5N - MAX 3000A 128-Macro 5ns CPLD | Altera

EPM3128ATC144-5N - MAX 3000A 128-Macro 5ns CPLD | Altera

EPM3128ATC144-5N ⚠ 最後購買機會

規格比較

參數 EPM3128ATI144-10 EPM3128ATC144-5N
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 NRND 最後購買
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD - Complex Programmable Logic Device
Usable Gates 2,500 2500
Macro Cells 128 —
Logic Array Blocks (LABs) 8 —
User I/Os 98 —
腳位數 144 —
封裝 TQFP-144 (FINE LINE) 144-pin TQFP (20x20 mm)
Supply Voltage (VCCINT) 3.3 V —
Pin-to-Pin Delay 10 ns (speed grade -10) —
Counter Frequency 98 MHz typical up to 227.3 MHz
Logic Family CMOS, EEPROM-based CMOS
Programming Interface IEEE 1149.1 JTAG (ISP) —
PCI Compliance PCI Local Bus Spec Rev 2.2 (speed grades -4 to -10) —
工作溫度 -40C to +85C (Industrial) 0C to 70C (Commercial)
安裝類型 Surface Mount (Gull-Wing TQFP) Surface Mount
RoHS 狀態 Compliant (lead-free TQFP) Compliant (lead-free)
Macrocells — 128
User I/O — 96
Pin-to-Pin Logic Delay — 5 ns
Supply Voltage (Core) — 3.3 V
I/O Logic Levels Supported — 5.0 V / 3.3 V / 2.5 V (MultiVolt)
In-System Programmability — Yes (3.3-V via JTAG)
JTAG Boundary Scan — IEEE Std 1149.1 compliant

資料表與資源

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