EPM3128ATI144-10 vs EPM3128ATC144-5N 对比

详细并排对比 EPM3128ATI144-10 出自 Altera 和 EPM3128ATC144-5N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM3128ATC144-5N EPM3128ATC144-5N - MAX 3000A 128-Macro 5ns CPLD | Altera

EPM3128ATC144-5N - MAX 3000A 128-Macro 5ns CPLD | Altera

EPM3128ATC144-5N ⚠ 最后一次采购

规格对比

参数 EPM3128ATI144-10 EPM3128ATC144-5N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 最后采购期
库存状态 有库存 有库存
单价(USD) $10.85 $13.75
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD - Complex Programmable Logic Device
Usable Gates 2,500 2500
Macro Cells 128 —
Logic Array Blocks (LABs) 8 —
User I/Os 98 —
引脚数量 144 —
封装 TQFP-144 (FINE LINE) 144-pin TQFP (20x20 mm)
Supply Voltage (VCCINT) 3.3 V —
Pin-to-Pin Delay 10 ns (speed grade -10) —
Counter Frequency 98 MHz typical up to 227.3 MHz
Logic Family CMOS, EEPROM-based CMOS
Programming Interface IEEE 1149.1 JTAG (ISP) —
PCI Compliance PCI Local Bus Spec Rev 2.2 (speed grades -4 to -10) —
工作温度 -40C to +85C (Industrial) 0C to 70C (Commercial)
安装类型 Surface Mount (Gull-Wing TQFP) Surface Mount
RoHS 状态 Compliant (lead-free TQFP) Compliant (lead-free)
Macrocells — 128
User I/O — 96
Pin-to-Pin Logic Delay — 5 ns
Supply Voltage (Core) — 3.3 V
I/O Logic Levels Supported — 5.0 V / 3.3 V / 2.5 V (MultiVolt)
In-System Programmability — Yes (3.3-V via JTAG)
JTAG Boundary Scan — IEEE Std 1149.1 compliant

数据手册与资源

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