EPM3128ATI144-10N vs EPM3128ATI144-7N 比較
詳細並排比較 EPM3128ATI144-10N 由 Intel 與 EPM3128ATI144-7N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EPM3128ATI144-10N - 128-Macrocell MAX 3000A CPLD, 10ns | Intel / Altera
EPM3128ATI144-10N NrndAltera
EPM3128ATI144-7N - 128 Macrocell CPLD, 129.9MHz, 3.3V | Altera MAX 3000A
EPM3128ATI144-7N ⚠ 最後購買機會規格比較
| 參數 | EPM3128ATI144-10N | EPM3128ATI144-7N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | 最後購買 |
| Family | MAX 3000A | MAX 3000A |
| Logic Type | CMOS EEPROM-based CPLD | — |
| Macrocells | 128 | 128 |
| Typical Gates | 2.5K | — |
| User I/Os | 96 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Internal Frequency | 98 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Output Bank Voltage (VCCIO) | 3.3 V or 2.5 V | — |
| 封裝 | 144-pin TQFP | 144-pin TQFP |
| 安裝類型 | Surface Mount | — |
| 工作溫度 | Industrial -40C to +85C | -40C to +85C (industrial) |
| In-System Programmability | Yes (IEEE Std. 1532 compliant) | — |
| JTAG / Boundary Scan | Yes (IEEE 1149.1) | — |
| Configuration Memory | Non-volatile EEPROM | — |
| RoHS 狀態 | Compliant | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Capacity | — | 2.5K gates |
| Maximum Frequency (fMAX) | — | 129.9 MHz |
| Pin-to-Pin Propagation Delay | — | 7.5 ns (speed grade -7) |
| User I/O Pins | — | 96 |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V / 2.5 V / 1.8 V |
| Programmable Logic Technology | — | CMOS EEPROM |
| Programming Interface | — | JTAG (IEEE Std 1149.1) in-system programmable |
| Terminal Pitch | — | 0.5 mm |
| JEDEC Package Code | — | S-PQFP-G144 |
| MultiVolt I/O | — | Yes (interfaces with 5.0V/3.3V/2.5V/1.8V logic) |