EPM3128ATI144-10N vs EPM3128ATI144-7N 对比

详细并排对比 EPM3128ATI144-10N 出自 Intel 和 EPM3128ATI144-7N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM3128ATI144-7N EPM3128ATI144-7N - 128 Macrocell CPLD, 129.9MHz, 3.3V | Altera MAX 3000A

EPM3128ATI144-7N - 128 Macrocell CPLD, 129.9MHz, 3.3V | Altera MAX 3000A

EPM3128ATI144-7N ⚠ 最后一次采购

规格对比

参数 EPM3128ATI144-10N EPM3128ATI144-7N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 最后采购期
库存状态 有库存 有库存
单价(USD) $10.32 $9.95
Family MAX 3000A MAX 3000A
Logic Type CMOS EEPROM-based CPLD —
Macrocells 128 128
Typical Gates 2.5K —
User I/Os 96 —
Propagation Delay (tPD) 10 ns —
Maximum Internal Frequency 98 MHz —
Supply Voltage (VCCINT) 3.3 V —
Output Bank Voltage (VCCIO) 3.3 V or 2.5 V —
封装 144-pin TQFP 144-pin TQFP
安装类型 Surface Mount —
工作温度 Industrial -40C to +85C -40C to +85C (industrial)
In-System Programmability Yes (IEEE Std. 1532 compliant) —
JTAG / Boundary Scan Yes (IEEE 1149.1) —
Configuration Memory Non-volatile EEPROM —
RoHS 状态 Compliant —
Device Type — CPLD (Complex Programmable Logic Device)
Logic Capacity — 2.5K gates
Maximum Frequency (fMAX) — 129.9 MHz
Pin-to-Pin Propagation Delay — 7.5 ns (speed grade -7)
User I/O Pins — 96
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 3.3 V / 2.5 V / 1.8 V
Programmable Logic Technology — CMOS EEPROM
Programming Interface — JTAG (IEEE Std 1149.1) in-system programmable
Terminal Pitch — 0.5 mm
JEDEC Package Code — S-PQFP-G144
MultiVolt I/O — Yes (interfaces with 5.0V/3.3V/2.5V/1.8V logic)

数据手册与资源

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