EPM3256AQC208-10N vs EPM3256AFC256-10N 比較
詳細並排比較 EPM3256AQC208-10N 由 Altera 與 EPM3256AFC256-10N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM3256AQC208-10N | EPM3256AFC256-10N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Series | MAX 3000A | — |
| Programmable Type | In-System Programmable (EEPROM) | — |
| Number of Macrocells | 256 | — |
| Number of Logic Elements/Blocks | 16 LABs | — |
| Usable Gates | 10,000 | 5,000 gates |
| Number of I/O Pins | 161 (158 user I/O per Arrow listing) | — |
| Propagation Delay (tpd) | 10 ns (max) | — |
| Maximum Counter Frequency | 227.3 MHz | 227.3 MHz |
| Supply Voltage - Internal | 3.0 V to 3.6 V (3.3 V typical) | — |
| 工作溫度 | 0C to +70C (Commercial) | 0 C to 70 C (commercial) |
| 封裝 / 外殼 | 208-BFQFP / 208-PQFP (28x28 mm) | — |
| 安裝類型 | Surface Mount | — |
| ISP Compliance | IEEE Std. 1532 | — |
| Boundary Scan | IEEE Std. 1149.1 (JTAG) | — |
| I/O Tolerance | 5 V tolerant, MultiVolt interface | — |
| RoHS 狀態 | [DATA_NEEDED: lead-free status - non-RoHS suffix 'N' typically indicates lead-free finish, but datasheet not present in data] | — |
| Family | — | MAX 3000A |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 256 |
| Maximum User I/O | — | 161 |
| Pin-to-Pin Logic Delay | — | 10 ns |
| Core Voltage | — | 3.3 V |
| I/O Logic Level Compatibility | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| Programmability | — | EEPROM, in-system programmable (ISP) |
| JTAG Interface | — | IEEE 1532 / JTAG (TDI, TDO, TMS, TCK) |
| 封裝 | — | 256-pin FineLine BGA |
| Logic Family | — | CMOS |
| PCI Compliance | — | PCI Local Bus Specification Rev 2.2 (at -10 grade) |