EPM3512AFC256-10 vs EPM3512AFC256-22 比較
詳細並排比較 EPM3512AFC256-10 由 Altera 與 EPM3512AFC256-22 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM3512AFC256-10 | EPM3512AFC256-22 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Usable Gates | 10,000 | — |
| Maximum I/O Pins | 208 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 87 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Voltage Tolerance | 5-V tolerant | — |
| Programmable Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG / IEEE Std. 1532) | — |
| 封裝 | 256-pin FBGA | FC-256 (FineLine BGA, 256 balls, 1.0 mm pitch) |
| 工作溫度範圍 | [DATA_NEEDED: industrial/commercial operating temperature range] | — |
| 腳位數 | 256 | — |
| 安裝類型 | Surface Mount | Surface Mount (BGA) |
| RoHS 狀態 | unknown | [DATA_NEEDED: RoHS compliance status] |
| Architecture | MAX (Multiple Array matriX) EEPROM-based | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Maximum User I/O Pins | — | 208 (typical for FC256 package) |
| Speed Grade | — | -22 (tPD ~22 ns) |
| Propagation Delay (tPD) | — | 22 ns |
| Supply Voltage VCCINT | — | 3.3 V |
| I/O Standards Supported | — | 2.5 V, 3.3 V, 5.0 V (VCCIO selectable) |
| In-System Programming | — | IEEE Std. 1532-compliant ISP via JTAG |
| Configuration Memory | — | On-chip EEPROM (non-volatile) |
| 工作溫度 | — | [DATA_NEEDED: operating temperature grade] |