EPM3512AFC256-5C vs EPM3512AFC256-10N 比較
詳細並排比較 EPM3512AFC256-5C 由 Altera 與 EPM3512AFC256-10N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM3512AFC256-5C - MAX 3000A CPLD, 512 Macrocells, 256-BGA | Altera
EPM3512AFC256-5C Obsolete規格比較
| 參數 | EPM3512AFC256-5C | EPM3512AFC256-10N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | 10000 |
| Maximum Operating Frequency | 95.2 MHz | — |
| Pin-to-Pin Delay (tPD) | 5 ns | 10 ns |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| I/O Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (banked MultiVolt I/O) | — |
| User I/O Pins | 212 (max) | 208 |
| 封裝 | 256-ball FBGA, 17 mm × 17 mm, 1.0 mm pitch | 256-ball FBGA (17 mm x 17 mm) |
| 工作溫度 | 0 °C to +70 °C (commercial, "C" grade) | — |
| Programming Interface | IEEE Std. 1532 / JTAG (4-wire) in-system programmable | — |
| 安裝類型 | Surface Mount | Surface Mount (BGA) |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Technology | EEPROM-based macrocell, non-volatile | CMOS EEPROM-based, non-volatile |
| Logic Array Blocks (LABs) | — | [DATA_NEEDED: number of LABs] |
| Operating Frequency (fMAX) | — | [DATA_NEEDED: fMAX MHz] |
| Setup Time (tSU) | — | 4.5 ns |
| VCCINT (Core Supply) | — | 3.3 V |
| VCCIO (I/O Supply) | — | 3.3 V or 2.5 V |
| Operating Temperature (Commercial) | — | 0 C to +70 C |
| ISP Interface | — | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| MSL 等級 | — | [DATA_NEEDED: MSL rating] |