EPM3512AFC256C vs EPM3256AFC256-10 比較
詳細並排比較 EPM3512AFC256C 由 Intel 與 EPM3256AFC256-10 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM3256AFC256-10 - 256-Macro CPLD MAX 3000A | Intel / Altera | FBGA-256
EPM3256AFC256-10 ⚠ 最後購買機會規格比較
| 參數 | EPM3512AFC256C | EPM3256AFC256-10 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | 最後購買 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | — |
| Logic Array Blocks (LABs) | 16 | 16 (16 macrocells each) |
| Maximum User I/Os | 208 | 161 |
| Dedicated Input Pins | 12 | — |
| 封裝 | 256-ball FineLine BGA (FC) | 256-ball FBGA (Fine-Line BGA) |
| 工作溫度 | 0C to +70C (Commercial) | 0°C to +70°C (Commercial) |
| Speed Grade | C (per datasheet ordering code) | — |
| Configuration Technology | EEPROM (non-volatile, instant-on) | — |
| Core Voltage | 3.3 V | — |
| I/O Standards Supported | MultiVolt: 5.0 V, 3.3 V, 2.5 V | — |
| JTAG Support | IEEE 1149.1 Boundary Scan | — |
| PCI Compliance | PCI SIG Local Bus Specification Revision 2.2 | — |
| Programming | In-system programmable via JTAG | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| 安裝類型 | Surface Mount | Surface Mount |
| Logic Family | — | CMOS (EEPROM-based) |
| Macro Cells | — | 256 |
| Usable Gates | — | 5,000 |
| Propagation Delay (tPD) | — | 10 ns |
| Internal Counter Frequency (fCNT) | — | 95.2 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage Tolerance | — | 5.0 V tolerant |
| In-System Programmability | — | Yes (3.3 V ISP via JTAG IEEE 1149.1) |
| Pitch | — | [DATA_NEEDED: BGA ball pitch] |