EPM3512AFI256-10N vs EPM3512ATC256-10N 比較
詳細並排比較 EPM3512AFI256-10N 由 Altera 與 EPM3512ATC256-10N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM3512AFI256-10N - 512-Macro MAX 3000A CPLD, 256-FBGA | Intel/Altera
EPM3512AFI256-10N ⚠ 最後購買機會規格比較
| 參數 | EPM3512AFI256-10N | EPM3512ATC256-10N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Series | EPM3512 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | CMOS EEPROM-based, MAX architecture | — |
| Number of Macrocells | 512 | — |
| Number of Logic Array Blocks (LABs) | 16 | — |
| Usable Gates | Up to 10,000 | — |
| Number of User I/O | 208 | — |
| Total Pins | 256 | — |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V (3.0 V to 3.6 V) | 3.3 V |
| I/O Supply Voltage (VCCIO) | 2.5 V or 3.3 V (5.0 V tolerant inputs) | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| MultiVolt I/O Support | 5.0 V / 3.3 V / 2.5 V | — |
| In-System Programmability | Yes - IEEE Std 1532 compliant | — |
| JTAG Boundary Scan | Yes - IEEE 1149.1 | — |
| Program Memory | EEPROM (non-volatile) | — |
| 封裝 | 256-ball FineLine BGA (FBGA-256) | FBGA-256 (FineLine BGA, 17x17 mm, 1.0 mm pitch) |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度範圍 | -40 °C to +85 °C (industrial) | — |
| RoHS 狀態 | Compliant | unknown |
| Speed Grade | -10 (10 ns tPD) | — |
| Macrocells | — | 512 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 208 |
| Propagation Delay (tPD1) | — | 10 ns |
| Programming Interface | — | JTAG (IEEE Std. 1149.1) - in-system programmable |
| 工作溫度 | — | 0 C to +70 C (commercial, "C" suffix) |
| Process Technology | — | 0.30 um CMOS EEPROM |
| Lead-Free | — | unknown |