EPM3512AQC208-7 vs EPM3512AQC208-10 比較
詳細並排比較 EPM3512AQC208-7 由 Intel 與 EPM3512AQC208-10 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EPM3512AQC208-7 - MAX 3000A CPLD, 512 Macrocells, 7.5ns, 208-PQFP | Intel
EPM3512AQC208-7 Nrnd規格比較
| 參數 | EPM3512AQC208-7 | EPM3512AQC208-10 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | 10,000 |
| Propagation Delay (tPD) | 7.5 ns | 7.5 ns |
| Counter Frequency (fCNT) | 116.3 MHz | — |
| User I/Os | 172 | 208 |
| Logic Elements / LEs | N/A (CPLD macrocell architecture) | — |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Standards Supported | 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) | — |
| 封裝 | 208-Pin PQFP (FQFP, gull-wing) | 208-pin PQFP |
| 工作溫度 | 0 C to +70 C (commercial) | 0C to +70 C (commercial) |
| Programming | In-System Programmable via JTAG (IEEE Std. 1532) | — |
| Process Technology | CMOS EEPROM, 0.30 um | — |
| RoHS 狀態 | Compliant | [DATA_NEEDED: RoHS status not in verified data] |
| Lead-Free | Yes | — |
| Logic Array Blocks (LABs) | — | 32 |
| Maximum Frequency (fCNT) | — | 116.3 MHz |
| Configuration Memory | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (IEEE Std. 1532) |
| JTAG Boundary Scan | — | Yes (IEEE 1149.1) |
| PCI Compliance | — | PCI Local Bus Spec Rev. 2.2 (-10 speed grade) |