EPM3512AQC20810N vs EPM3512AQI20810 比較

詳細並排比較 EPM3512AQC20810N 由 Altera 與 EPM3512AQI20810 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM3512AQC20810N EPM3512AQI20810
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 NRND NRND
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macro Cells 512 —
Usable Gates 10,000 10,000
User I/Os 172 —
Logic Array Blocks (LABs) 16 16 (32 macrocells each)
Propagation Delay (tPD) 10 ns —
Core Voltage (VCCINT) 3.3 V —
I/O Voltage (VCCIO) 3.3 V (5.0 V tolerant I/O) —
封裝 208-pin PQFP (Plastic Quad Flat Pack) 208-pin PQFP (PQ208)
Configuration Memory EEPROM (non-volatile, instant-on) —
Programming Interface JTAG (IEEE 1149.1 / IEEE 1532 ISP) —
Maximum Frequency [DATA_NEEDED: fMAX] —
工作溫度 [DATA_NEEDED: industrial/commercial grade range] -40 °C to +85 °C (Industrial, "I" suffix)
RoHS 狀態 [DATA_NEEDED: lead-free/RoHS status] —
安裝類型 Surface Mount Surface Mount
MSL 等級 [DATA_NEEDED: MSL rating] —
Macrocells — 512
Maximum User I/O Pins — 172
Pin-to-Pin Propagation Delay (tPD) — 10 ns
Internal fMAX (logic feedback) — 87 MHz
Supply Voltage (VCCINT) — 3.0 V to 3.6 V
MultiVolt I/O Interface — 1.8 V / 2.5 V / 3.3 V / 5.0 V compatible
Process Technology — 0.30 µm CMOS EEPROM
In-System Programmability — IEEE Std. 1149.1 JTAG + IEEE Std. 1532
Lead-Free / RoHS — Contains lead / RoHS non-compliant (per Altera datasheet marking)

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