EPM3512ATC144 vs EPM3256ATC144-7N 比較

詳細並排比較 EPM3512ATC144 由 Altera 與 EPM3256ATC144-7N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EPM3256ATC144-7N EPM3256ATC144-7N - MAX 3000A CPLD 256 Macro 7.5ns | Altera

EPM3256ATC144-7N - MAX 3000A CPLD 256 Macro 7.5ns | Altera

EPM3256ATC144-7N ⚠ 最後購買機會

規格比較

參數 EPM3512ATC144 EPM3256ATC144-7N
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 NRND 最後購買
Family MAX 3000A MAX 3000A
Macrocells 512 —
Logic Array Blocks (LABs) 16 —
Maximum User I/O Pins 212 —
封裝 TQFP-144 (20x20 mm) 144-pin TQFP
Core Supply Voltage 3.3 V —
Programming Technology EEPROM (in-system programmable) —
JTAG Interface IEEE Std. 1149.1 (4-pin) —
Maximum Frequency 116 MHz —
Propagation Delay (tPD) [DATA_NEEDED: tPD in ns] 7.5 ns
Product Terms per Macrocell 32 (expandable) —
I/O Standards LVTTL, LVCMOS, 2.5 V/3.3 V/5 V tolerant —
工作溫度 0C to +70C (commercial) 0C to +70C (Commercial)
安裝類型 Surface Mount Surface Mount
MSL 等級 3 —
RoHS 狀態 Compliant (lead-free suffix variants available) Compliant
Device Type — CPLD - Complex Programmable Logic Device
Macro Cells — 256
Logic Gates (usable) — 5,000
Number of Logic Array Blocks (LABs) — 16
User I/Os — 116
Maximum Internal Frequency — 126.6 MHz
Supply Voltage (VCCIO) — 3.0 V to 3.6 V
Programmable Logic Technology — CMOS EEPROM-based
In-System Programmable (ISP) — Yes (3.3 V)
Logic Family — CMOS
JTAG Support — IEEE 1149.1 boundary-scan

資料表與資源

瀏覽所有產品 建立 BOM 索取報價