EPM5016DC-17 vs EPM5016DC-15 比較
詳細並排比較 EPM5016DC-17 由 Altera 與 EPM5016DC-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5016DC-17 | EPM5016DC-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Macrocells | 16 | 16 |
| Logic Elements | [DATA_NEEDED: LE count for MAX 5000 family] | — |
| User I/O Pins (max) | 24 | — |
| Propagation Delay (tPD) | 17 ns | — |
| Counter Frequency (fCNT) | 67 MHz | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V |
| I/O Standard | TTL-compatible | — |
| Process Technology | 0.75 micron CMOS EEPROM | CMOS EPROM |
| 封裝 | Ceramic DIP-24 (DC suffix) | Ceramic DIP-24 (windowed) |
| 腳位數 | 24 | — |
| 安裝類型 | Through-hole | Through-Hole |
| 工作溫度 | 0C to +70C (commercial) | 0 °C to 70 °C (commercial) |
| In-System Programmability | Yes (ByteBlaster / BitBlaster) | — |
| Configuration Memory | On-chip EEPROM (non-volatile) | Non-volatile UV-erasable EPROM |
| RoHS 狀態 | [DATA_NEEDED: confirmed compliance status from manufacturer] | [DATA_NEEDED: RoHS status - pre-RoHS era part, likely non-compliant] |
| Device Family | — | MAX 5000 |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 2 |
| Dedicated Inputs | — | 4 |
| User I/O Pins | — | 12 |
| Pin-to-Pin Delay (tpd) | — | 15 ns |
| Maximum Frequency (fmax) | — | 71 MHz |
| Programming Voltage (VPP) | — | 12.75 V |
| Lead Finish | — | [DATA_NEEDED: lead-free status] |