EPM5016DC-17 vs EPM5016LC-17 比較
詳細並排比較 EPM5016DC-17 由 Altera 與 EPM5016LC-17 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5016DC-17 | EPM5016LC-17 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 EPLD |
| Macrocells | 16 | 16 |
| Logic Elements | [DATA_NEEDED: LE count for MAX 5000 family] | — |
| User I/O Pins (max) | 24 | — |
| Propagation Delay (tPD) | 17 ns | 17 ns |
| Counter Frequency (fCNT) | 67 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| I/O Standard | TTL-compatible | — |
| Process Technology | 0.75 micron CMOS EEPROM | — |
| 封裝 | Ceramic DIP-24 (DC suffix) | Windowed Ceramic DIP (LC) |
| 腳位數 | 24 | — |
| 安裝類型 | Through-hole | — |
| 工作溫度 | 0C to +70C (commercial) | [DATA_NEEDED: temperature grade] |
| In-System Programmability | Yes (ByteBlaster / BitBlaster) | — |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| RoHS 狀態 | [DATA_NEEDED: confirmed compliance status from manufacturer] | [DATA_NEEDED: RoHS compliance] |
| Technology | — | CMOS, UV-erasable |
| Product Terms | — | 160 |
| Dedicated Inputs | — | 7 |
| I/O Pins | — | 8 |
| Total Input Pins | — | 16 |
| Outputs | — | 8 |
| External Clock Inputs | — | 1 |
| Architecture | — | PAL-type with Programmable Interconnect Array (PIA) |
| 供應電壓 | — | [DATA_NEEDED: VCC range] |
| Logic Compatibility | — | TTL/CMOS |